收藏本站
Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Table 2–1. Generated Files (Part 2 of 2)
Filename
(Note 1) (2)
Description
2–17
remove_constraints_for_ <variation name> .tcl
top_ddr_settings.txt
top_pre_compile_ddr_timing_summary.txt
verify_timing_for_ <variation name> .tcl
The remove constraints script for the variation.
Critical settings file that stores the custom variation’s
parameters. IP Toolbench uses this file to generate the add
constraints script. The verify timing script and the DDR Timing
Wizard also read this file.
Log file that stores the results of the precompilation system
timing analysis.
The verify timing script.
Notes to Table 2–1 :
(1) <project name> is the name of the Quartus II project top-level entity.
(2) <variation name> is the name you give to the controller you create with the Megawizard.
2. After you review the generation report, click Exit to close IP Toolbench.
1
The Quartus II IP File ( .qip ) is a file generated by the MegaWizard interface or SOPC
Builder that contains information about a generated IP core. You are prompted to add
this .qip file to the current Quartus II project at the time of file generation. In most
cases, the .qip file contains all of the necessary assignments and information required
to process the core or system in the Quartus II compiler. Generally, a single .qip file is
generated for each MegaCore function and for each SOPC Builder system. However,
some more complex SOPC Builder components generate a separate .qip file, so the
system .qip file references the component .qip file.
You have finished the walkthrough. Now, simulate the example design (see
“Simulate the Example Design” on page 2–17 ), edit the PLL(s), and compile (refer to
“Compile the Example Design” on page 2–22 ).
Simulate the Example Design
You can simulate the example design with the IP Toolbench-generated IP functional
simulation models. IP Toolbench generates a VHDL or Verilog HDL testbench for
your example design, which is in the testbench directory in your project directory.
f
For more information on the testbench, refer to “Example Design” on page 3–16 .
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. The instructions for the ModelSim simulator are different to
other simulators.
Simulating With the ModelSim Simulator
To simulate the example design with the ModelSim ? simulator, follow these steps:
1. Obtain a memory model that matches your chosen parameters and save it to the
< directory name > testbench directory. For example, you can download a Micron
memory model from the Micron web site at www.micron.com .
? March 2009
Altera Corporation
DDR and DDR2 SDRAM Controller Compiler User Guide
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
IP-SLITE2 IP SERIALLITE II
IP-SRAM/QDRII IP QDRII SRAM CONTROLLER
IP-VITERBI/SS IP VITERBI LOW-SPEED
IP4220CZ6,125 IC USB DUAL ESD PROTECT 6TSOP
IPA-66-1-600-10.0-A-01-T CIRC BRKR 10A 2POLE SCREW TERM
IPR-CSC IP COLOR SPACE CONVERTER RENEW
IPR-ED8B10B IP 8B10B ENCODER/DECODER RENEW
IPS-VIDEO IP VIDEO/IMAGE PROCESSING SUITE
相关代理商/技术参数
IP-SDRAM/DDR3 功能描述:开发软件 DDR3 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR 功能描述:开发软件 DDR SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/HPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-SDRAM/LPDDR2 功能描述:开发软件 DDR2 SDRAM Control MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPSE.4.33SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.33SM600 GLASS FIBER (MIN ORDER 50)
IPSE.4.62SM600 制造商:Banner Engineering 功能描述:FIBER IPSE.4.62SM600 GLASS FIBER (MIN ORDER 50)
IPS-EMBEDDED 功能描述:开发软件 Embedded IP Suite MegaCore RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPS-EVAL-EH-01 功能描述:ENERGY HARVESTING BOARD RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:THINERGY® 标准包装:1 系列:- 主要目的:数字电位器 嵌入式:- 已用 IC / 零件:AD5258 主要属性:- 次要属性:- 已供物品:板 相关产品:AD5258BRMZ1-ND - IC POT DGTL I2C1K 64P 10MSOPAD5258BRMZ10-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ100-ND - IC POT DGTL I2C 100K 64P 10MSOPAD5258BRMZ50-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ1-R7-ND - IC POT DGTL I2C 1K 64P 10MSOPAD5258BRMZ10-R7-ND - IC POT DGTL I2C 10K 64P 10MSOPAD5258BRMZ50-R7-ND - IC POT DGTL I2C 50K 64P 10MSOPAD5258BRMZ100-R7-ND - IC POT DGTL I2C 100K 64P 10MSOP